In order to fabricate integrated circuits, layers provided with different electrical properties are usually applied to semiconductor substrates (wafers) and patterned lithographically. Lithographic patterning may include applying a photosensitive resist, exposing the resist with a desired structure for the relevant plane, developing it, and then transferring the resist mask into the underlying layer in an etching step.
As the integration densities of integrated circuits continually increase, there is also an increase in the requirements made of the positional accuracy of a structure to be projected onto the semiconductor substrate. Particularly when prior planes have already been transferred into underlying layers, e.g., in a lithographic projection step, it is necessary to account for stricter tolerance limits with regard to the reciprocal orientation of the structure that is currently to be projected onto the substrate relative to the structures of the aforementioned prior planes, in order to ensure the functionality of the circuit.
Therefore, before the start of the respective exposures, alignment sequences are provided for the lithographic projection step, which may be performed, e.g., in a wafer stepper or scanner. The alignment marks are typically arranged in the edge regions of the masks providing the relevant structure. During the exposure, the alignment marks are transferred in the sawing kerf that separates the individual exposure fields on the wafer. The alignment marks make it possible to determine the position of the structures formed on the wafer or, by determining the positioning of the alignment marks, it is possible to deduce the precise positioning and orientation of the structure for the integrated circuit.
The orientation or alignment of the substrate in the exposure device with respect to the projection optics (i.e., the projection lenses, the mask that is to be projected in each case, diaphragms and also the illumination source, etc.) is carried out by comparing the alignment marks with reference marks. Such reference marks are often inserted via the lens system with respect to a detector.
The way in which the alignment method is specifically carried out depends on the device manufacturers. An offset of the actual alignment mark position with respect to the ideal position of the reference mark is ascertained on the basis of the mark comparison. Consequently, the wafer that is generally deposited onto a substrate holder can be corrected in terms of its position, so that the subsequent exposure can be performed with high positional accuracy.
A problem to which little consideration has been given hitherto in this context is proposed by the differing degree of positional accuracy of different structure pattern proportions that can be achieved within an exposure field. Reasons for this are, in particular, lens imaging errors such as, for example, the distortions called coma, three-leaf clover, astigmatism, etc., and are generally referred to as aberration errors.
Furthermore, process influences lead to a deviation of the alignment mark from the ideal position, which may arise, for example, during chemical mechanical polishing or metal deposition in a sputtering installation.
An effect that is to be emphasized as particularly problematic here is that the size of the imaging error of a structure depends on the respective form, orientation and size of the structure. It thus happens that, for example, dense line/gap structures having very small structure dimensions are provided with a different offset with respect to an ideal position during an exposure with a perfect lens than for example the alignment marks that generally have very large dimensions.
In such cases, the abovementioned conclusion of the positions of the respectively imaged structures drawn from the position determined for the alignment mark during alignment may be beset by errors. This is more applicable as the structures or structure elements differ in size, form, and orientation from the alignment marks.
Most device manufacturers embody alignment marks as arrangements of elongate, parallel bars. Such bars are nowadays usually embodied with structure widths of more than 1 μm. Dense line/gap patterns such as are formed, for instance, in the area of fabrication of random access memories (DRAM) have line widths of 70, 90, or 110 nm.
In the area of alignment methods, i.e., during alignment of a wafer in the exposure device, for two successively exposed planes on a test substrate, a first offset is measured between a first and second overlay measurement mark of the two planes and a second offset is measured between a first and a second element of structures of the respective planes. The two elements have a width near to the resolution limit of the exposure device. The two elements are thus subject to a different imaging error on account of lens distortions and the measurement marks. The offset between the first and second offsets is determined by an optical measurement method and added as correction for the exposure position determined by alignment mark comparison during the alignment of a substrate that is subsequently to be exposed, so that the two structures, instead of the alignment or overlay measurement marks, are aligned with one another with high accuracy.
In this case, however, determining the positional accuracy error by test exposures necessitates the production of a plurality of special test substrates which permit a determination of the positional inaccuracies for two layers laying one above the other. As a result, the determination of the positional inaccuracies for the layers of the integrated circuit is very time-consuming, particularly when evaluating a new process line.
A method for simply determining of the positioning errors for each layer for an integrated circuit having one layer or having a plurality of layers is desirable.